Girish Ratanpal is experienced in preparing and prosecuting patent applications in the fields of computer networking, optical networks, Fiber-Channel networks and switches, electronic design automation (EDA), hybrid power supplies, vehicle battery systems, display devices, micro-electro-mechanical (MEMS) devices, optical devices, communication, deep learning, signal processing, analog and digital circuits, medical devices, and consumer electronics, including but not limited to storage area networks, audio and video conferencing systems, and implantable cochlear and spinal stimulators.

He has also assisted in patent infringement and invalidity analysis related to complex technologies involving computer networks, encryption, memory systems, display devices, heat exchange controllers, oil field exploration, and power conversion electronics and re-examinations, patent portfolio analysis, and freedom to operate analysis.

Girish has authored three technical publications, including IEEE Transactions on Secure and Dependable Computing and IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. In addition to his publication list, he has presented at the Great Lakes Symposium on VLSI.

Seasoned in working with university and corporate clients, Girish has also worked with startups, including participating in the MassChallenge accelerator program in Boston.

Before JMIN

Prior to joining JMIN, Girish was a Senior Associate at Innovators Legal for three years. Before that, he spent more than fourteen years as a technical specialist at law firms in Houston and Boston.

Practice Areas


  • Suffolk University Law School, Juris Doctor
  • University of Virginia, Ph.D. in Electrical Engineering
  • State University of New York at Binghamton Master of Science in Electrical Engineering
  • Pune University, Bachelor of Engineering in Industrial Electronics


  • U.S. Patent and Trademark Office
  • Massachusetts

Published Work

  • “An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks,” G.B. Ratanpal, R.D. Williams, and T.N. Blalock, IEEE Transactions on Secure and Dependable Computing 1(3), 179-189 (2004).
  • “A VLSI Crossbar Switch with Wrapped Wave Front Arbitration,” J.G. Delgado-Frias and G.B. Ratanpal, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 50(1), 135-41 (2003).
  • “A VLSI Wrapped Wave Front Arbiter for Crossbar Switches,” J.G. Delgado-Frias and G.B. Ratanpal, Proceedings of the 11th Great Lakes Symposium on VLSI, West Lafayette IN, 85-88 (2001)